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ds07-13737-2e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90350 series mb90f352/s, mb90352/s n n n n description the mb90350-series with 1 channel full-can* interface and flash rom is especially designed for automotive and industrial applications. its main feature is the on-board can interface, which conform to v2.0 part a and part b, while supporting a very flexible message buffer scheme and so offering more functions than a normal full can approach. with the new 0.35 m m cmos technology, fujitsu now offers on-chip flash-rom program memory up to 128 kbytes. an internal voltage booster removes the necessity for a second programming voltage. an on board voltage regulator provides 3 v to the internal mcu core. this creates a major advantage in terms of emi and power consumption. the internal pll clock frequency multiplier provides an internal 42 ns instruction cycle time from an external 4 mhz clock. the unit features a 4 channel output compare unit and 6 channel input capture unit with 2 separate 16-bit free running timers. 2 channels uart constitute additional functionality for communication purposes. * : controller area network (can) - license of robert bosch gmbh note : f 2 mc stands for fujitsu flexible microcontroller, a registered trademark of fujitsu limited. n n n n pac k ag e 64-pin plastic lqfp (fpt-64p-m09)
mb90350 series 2 n n n n features clock ? built-in pll clock frequency multiplication circuit ? selection of machine clocks (pll clocks) is allowed among frequency division by two on oscillation clock, and multiplication of 1 to 6 times of oscillation clock (for 4 mhz oscillation clock, 4 mhz to 24 mhz). ? operation by sub-clock (up to 50 khz : 100 khz oscillation clock divided by two) is allowed. (devices without s-suffix only) ? minimum execution time of instruction : 42 ns (when operating with 4-mhz oscillation clock, and 6-time multi- plied pll clock). ? built-in clock modulation circuit 16 mbyte cpu memory space ? 24-bit internal addressing external bus interface ? 4 mbyte external memory space instruction system best suited to controller ? wide choice of data types (bit, byte, word, and long word) ? wide choice of addressing modes (23 types) ? enhanced multiply-divide instructions and reti instructions ? enhanced high-precision computing with 32-bit accumulator instruction system compatible with high-level language (c language) and multitask ? employing system stack pointer ? enhanced various pointer indirect instructions ? barrel shift instructions increased processing speed ? 4-byte instruction queue powerful interrupt function ? powerful 8-level, 34-condition interrupt feature ? up to 8 channels external interrupts are supported automatic data transfer function independent of cpu ? extended intelligent i/o service function (ei 2 os) : up to 16 channels ? dma : up to 16 channels low power consumption (standby) mode ? sleep mode (a mode that halts cpu operating clock) ? main timer mode (a timebase timer mode switched from the main clock mode) ? pll timer mode (a timebase timer mode switched from the pll clock mode) ? watch mode (a mode that operates sub clock and clock timer only) ? stop mode (a mode that stops oscillation clock and sub clock) ? cpu blocking operation mode process ?cmos technology i/o port ? general-purpose input/output port (cmos output) - 49 ports (devices without s-suffix) - 51 ports (devices with s-suffix) (continued)
mb90350 series 3 (continued) timer ? time-base timer, clock timer, watchdog timer : 1 channel ? 8/16-bit ppg timer : 8-bit 10 channels, or 16-bit 6 channels ? 16-bit reload timer : 4 channels ? 16- bit input/output timer - 16-bit free run timer : 2 channels (frt0 : icu0/1, frt1 : icu 4/5/6/7, ocu 4/5/6/7) - 16- bit input capture: (icu) : 6 channels - 16-bit output compare : (ocu) : 4 channels full-can interface : 1 channel ? compliant with ver2.0a and ver2.0b can specifications ? flexible message buffering (mailbox and fifo buffering can be mixed) ? can wake-up function uart (lin/sci) : 2 channels ? equipped with full-duplex double buffer ? clock-asynchronous or clock-synchronous serial transmission is available i 2 c interface* : 1 channel ? up to 400 kbit/s transfer rate dtp/external interrupt : 8 channels, can wakeup : 1 channel ? module for activation of extended intelligent i/o service (ei 2 os), dma, and generation of external interrupt. delay interrupt generator module ? generates interrupt request for task switching. 8/10-bit a/d converter : 15 channels ? resolution is selectable between 8-bit and 10-bit. ? activation by external trigger input is allowed. ? conversion time : 3 m s (at 24-mhz machine clock, including sampling time) program patch function ? address matching detection for 6 address pointers. internal voltage regulator ? supports 3 v mcu core, offering low emi and low power consumption figures programmable input levels ? automotive/cmos-schmitt (initial level is automotive in single chip mode) ? ttl level (initial level for external bus mode) flash security function ? protects the content of flash (flash device only) * : i 2 c license : purchase of fujitsu i 2 c components conveys a license under the philips i 2 c patent rights to use, these com- ponents in an i 2 c system provided that the system conforms to the i 2 c standard specification as defined by philips.
mb90350 series 4 n n n n product lineup (continued) part number parameter mb90f352/s, mb90352/s* 1 mb90v340a-101/102 cpu f 2 mc-16lx cpu system clock on-chip pll clock multiplier ( 1, 2, 3, 4, 6, 1/2 when pll stops) minimum instruction execution time : 42 ns (4 mhz osc. pll 6) rom boot-block, flash memory 128 kbytes external ram 4 kbytes 30 kbytes emulator-specific power supply* 2 ? yes technology 0.35 m m cmos with regulator for internal power supply + flash memory charge pump for programming voltage 0.35 m m cmos with regulator for internal power supply operating voltage range 3.5 v - 5.5 v : at normal operating (not using a/d converter) 4.0 v - 5.5 v : at using a/d converter/flash programming 4.5 v - 5.5 v : at using external bus 5 v 10 % temperature range - 40 c to + 105 c (125 c up to 16 mhz machine clock) ? package lqfp-64 pga-299 uart 2 channels 3 channels wide range of baud rate settings using a dedicated reload timer special synchronous options for adapting to different synchronous serial protocols lin functionality working either as master or slave lin device i 2 c (400 kbit/s) 1 channel 1 channel a/d converter 15 channels 10-bit or 8-bit resolution conversion time : min 3 m s include sample time (per one channel) 16-bit reload timer (4 channels) operation clock frequency : fsys/2 1 , fsys/2 3 , fsys/2 5 (fsys = machine clock frequency) supports external event count function 16-bit i/o timer (2 channels) signals an interrupt when overflowing supports timer clear when a match with output compare (channel 0, 4) operation clock freq. : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 , fsys/2 5 , fsys/2 6 , fsys/2 7 (fsys = machine clock freq.) i/o timer 0 (clock input frck0) corresponds to icu 0/1 i/o timer 1 (clock input frck1) corresponds to icu 4/5/6/7, ocu 4/5/6/7 16-bit output compare (4 channels) signals an interrupt when 16-bit i/o timer match output compare registers. a pair of compare registers can be used to generate an output signal. 16-bit input capture (6 channels) rising edge, falling edge or rising & falling edge sensitive signals an interrupt upon external event
mb90350 series 5 *1 : the devices are under development. *2 : it is setting of jumper switch (tool v cc ) when emulator (mb2147-01) is used. please refer to the emulator hardware manual about details. *3 : embedded algorithm is a trade mark of advanced micro devices inc. part number parameter mb90f352/s, mb90352/s* 1 mb90v340a-101/102 8/16-bit programmable pulse generator 6 channels (16-bit) / 10 channels (8-bit) supports 8-bit and 16-bit operation modes 8-bit reload counters 12 8-bit reload registers for l pulse width 12 8-bit reload registers for h pulse width 12 a pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler + 8-bit reload counter operation clock freq. : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 or 128 m s@fosc = 4 mhz (fsys = machine clock frequency, fosc = oscillation clock frequency) can interface 1 channel 2 channels conforms to can specification version 2.0 part a and b automatic re-transmission in case of error automatic transmission responding to remote frame prioritized 16 message buffers for data and ids supports multiple messages flexible configuration of acceptance filtering : full bit compare/full bit mask/two partial bit masks supports up to 1 mbps external interrupt (8 channels) can be used rising edge, falling edge, starting up by h/l level input, external interrupt, extended intelligent i/o services (ei 2 os) and dma d/a converter ? 1 channel subclock (up to100 khz) devices with s-suffix and mb90v340a-102 : without subclock devices without s-suffix and mb90v340a-101 : with subclock i/o ports virtually all external pins can be used as general purpose i/o port all push-pull outputs bit-wise settable as input/output or peripheral signal settable as cmos schmitt trigger/ automotive inputs (default) ttl input level settable for external bus (30 terminals only for external bus) flash memory supports automatic programming, embedded algorithm tm * 3 write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of erase cycles : 10,000 times data retention time : 10 years boot block configuration erase can be performed on each block block protection with external programming voltage flash security feature for protecting the content of the flash ?
mb90350 series 6 n n n n pin assignments ? mb90f352/s, mb90352/s (top view) (lqfp-64p) (fpt-64p-m09) * : mb90f352/352 : x0a, x1a mb90f352s/352s : p40, p41 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 avcc p61/an1 p60/an0 p37/clk/out7 p36/rdy/out6 p35/hak /out5 p34/hrq/out4 p32/wrl /wr /int10r p31/rd /in5 p30/ale/in4 p45/scl0/frck1 p44/sda0/frck0 p25/a21/in1/adtg c vcc p33/wrh 10 11 12 13 14 15 16 1234567 9 8 p10/ad08/tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int13 p04/ad04/int12 p03/ad03/int11 p02/ad02/int10 p01/ad01/int9 p00/ad00/int8 md0 md1 md2 p41/x1a* p40/x0a* vss p43/in7/tx1 vss x0 x1 rst p24/a20/in0 p23/a19/ppgf(e) p22/a18/ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9(8) p17/ad15 p16/ad14 p15/ad13 p14/ad12/sck3 p13/ad11/sot3 p12/ad10/sin3/int11r p11/ad09/tot1 avss avrh p64/an4/ppg8(9) p65/an5/ppga(b) p66/an6/ppgc(d) p67/an7/ppge(f) p50/an8/sin2 p51/an9/sot2 p52/an10/sck2 p53/an11/tin3 p56/an14 p55/an13 p54/an12/tot3 p62/an2/ppg4(5) p63/an3/ppg6(7) p42/in6/rx1/int9r
mb90350 series 7 n n n n pin description (continued) pin no. pin name circuit type function lqfp64* 46 x1 a oscillation output pin. 47 x0 oscillation input pin. 45 rst e reset input pin. 3 to 8 p62 to p67 i general purpose i/o ports. an2 to an7 analog input pins for a/d converter. ppg4, 6, 8, a, c, e output pins for ppgs. 9 p50 o general purpose i/o port. an8 analog input pin for a/d converter. sin2 serial data input pin for uart2. 10 p51 i general purpose i/o port. an9 analog input pin for a/d converter. sot2 serial data output pin for uart2. 11 p52 i general purpose i/o port. an10 analog input pin for a/d converter. sck2 serial data output pin for uart2. 12 p53 i general purpose i/o port. an11 analog input pin for a/d converter. tin3 event input pin for reload timer3. 13 p54 i general purpose i/o port. an12 analog input pin for a/d converter. tot3 output pin for reload timer3. 14, 15 p55, p56 i general purpose i/o ports. an13, an14 analog input pins for a/d converter. 16 p42 f general purpose i/o port. in6 data sample input pin for input capture icu6. rx1 rx input pin for can1. int9r external interrupt request input pin for int9. 17 p43 f general purpose i/o port. in7 data sample input pin for input capture icu7. tx1 tx output pin for can1. 19, 20 p40, p41 f general purpose i/o ports (devices with s-suffix and mb90v340a-101) . x0a, x1a b oscillation input pins for sub clock (devices without s-suffix and mb90v340a-102) .
mb90350 series 8 (continued) pin no. pin name circuit type function lqfp64* 24 to 31 p00 to p07 g general purpose i/o ports.the register can be set to select whether to use a pull-up resistor.this function is enabled in single-chip mode. ad00 to ad07 input/output pins of external address data bus lower 8 bit. this function is enabled when the external bus is enabled. int8 to int15 external interrupt request input pins for int8 to int15. 32 p10 g general purpose i/o port.the register can be set to select whether to use a pull-up resistor.this function is enabled in single-chip mode. ad08 input/output pin for external bus address data bus bit 8. this function is enabled when external bus is enabled. tin1 event input pin for reload timer1. 33 p11 g general purpose i/o.the register can be set to select whether to use a pull-up resistor.this function is enabled in single-chip mode. ad09 input/output pin for external bus address data bus bit 9. this function is en- abled when external bus is enabled. tot1 output pin for reload timer1. 34 p12 n general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad10 input/output pin for external bus address data bus bit 10. this function is enabled when external bus is enabled. sin3 serial data input pin for uart3. int11r external interrupt request input pin for int11 35 p13 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad11 input/output pin for external bus address data bus bit 11. this function is enabled when external bus is enabled. sot3 serial data output pin for uart3. 36 p14 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad12 input/output pin for external bus address data bus bit 12. this function is enabled when external bus is enabled. sck3 clock input/output pin for uart3. 37 p15 n general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad13 input/output pin for external bus address data bus bit 13. this function is enabled when external bus is enabled. 38 p16 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad14 input/output pin for external bus address data bus bit 14. this function is enabled when external bus is enabled.
mb90350 series 9 (continued) pin no. pin name circuit type function lqfp64* 39 p17 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad15 input/output pin for external bus address data bus bit 15. this function is enabled when external bus is enabled. 40 to 43 p20 to p23 g general purpose i/o ports. the register can be set to select whether to use a pull-up resistor. in external bus mode, the pin is enabled as a general- purpose i/o port when the corresponding bit in the external address output control register (hacr) is 1. a16 to a19 output pins for a16 to a19 of the external address bus. when the corresponding bit in the external address output control register (hacr) is 0, the pins are enabled as high address output pins a16 to a19. ppg9, ppgb, ppgd, ppgf output pins for ppgs. 44 p24 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. in external bus mode, the pin is enabled as a general- purpose i/o port when the corresponding bit in the external address output control register (hacr) is 1. a20 output pins for a20 of the external address bus. when the corresponding bit in the external address output control register (hacr) is 0, the pin is enabled as high address output pins a20. in0 data sample input pin for input capture icu0. 51 p25 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. in external bus mode, the pin is enabled as a general- purpose i/o port when the corresponding bit in the external address output control register (hacr) is 1. a21 output pin for a21 of the external address bus. when the corresponding bit in the external address output control register (hacr) is 0, the pin is en- abled as high address output pin a21. in1 data sample input pin for input capture icu1. adtg trigger input pin for a/d converter. 52 p44 h general purpose i/o port sda0 serial data i/o pin for i 2 c 0 frck0 input pin for the 16-bit i/o timer 0 53 p45 h general purpose i/o port. scl0 serial clock i/o pin for i 2 c 0 frck1 input for the 16-bit i/o timer 1 54 p30 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ale address latch enable output pin. this function is enabled when external bus is enabled. in4 data sample input pin for input capture icu4.
mb90350 series 10 (continued) pin no. pin name circuit type function lqfp64* 55 p31 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. rd read strobe output pin for data bus. this function is enabled when external bus is enabled. in5 data sample input pin for input capture icu5. 56 p32 g general purpose i/o port. the register can be set to select whether to use pull-up resistor. this function is enabled either in single-chip mode or with the wr /wrl pin output disabled. wr /wrl write strobe output pin for the data bus. this function is enabled when both the external bus and the wr /wr l pin output are enabled. wrl is used to write-strobe 8 lower bits of the data bus in 16-bit access. wr is used to write-strobe 8 bits of the data bus in 8-bit access. int10r external interrupt request input pin for int10. 57 p33 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or with the wrh pin output disabled. wrh write strobe output pin for the 8 higher bits of the data bus. this function is enabled when the external bus is enabled, when the external bus 16-bit mode is selected, and when the wrh output pin is enabled. 58 p34 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or with the hold function disabled. hrq hold request input pin. this function is enabled when both the external bus and the hold function are enabled. out4 waveform output pin for output compare ocu4. 59 p35 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or with the hold function disabled. hak hold acknowledge output pin. this function is enabled when both the external bus and the hold function are enabled. out5 waveform output pin for output compare ocu5. 60 p36 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or with the external ready function disabled. rdy ready input pin. this function is enabled when both the external bus and the external ready function are enabled. out6 waveform output pin for output compare ocu6. 61 p37 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or with the clk output disabled. clk clk output pin. this function is enabled when both the external bus and clk output are enabled. out7 waveform output pin for output compare ocu7.
mb90350 series 11 (continued) * : fpt-64p-m09 pin no. pin name circuit type function lqfp64* 62, 63 p60, p61 i general purpose i/o ports. an0, an1 analog input pins for a/d converter. 64 av cc kv cc power input pin for analog circuits. 2 avrh l reference voltage input for the a/d converter. this power supply must be turned on or off while a voltage higher than or equal to avrh is applied to av cc . 1av ss kv ss power input pin for analog circuits. 22, 23 md1, md0 c input pins for specifying the operating mode. 21 md2 d input pins for specifying the operating mode. 49 v cc ? power (3.5 v to 5.5 v) input pin. 18, 48 v ss ? power (0 v) input pins. 50 c k this is the power supply stabilization capacitor pin. it should be connected to a higher than or equal to 0.1 m f ceramic capacitor.
mb90350 series 12 n n n n i/o circuit type (continued) type circuit remarks a oscillation circuit ? high-speed oscillation feedback resistor = approx. 1 m w b oscillation circuit ? low-speed oscillation feedback resistor = approx. 10 m w c mask rom device: ? cmos hysteresis input pin flash device: ? cmos input pin d mask rom device: ? cmos hysteresis input pin ? pull-down resistor valule: approx. 50 k w flash device: ? cmos input pin ? no pull-down e cmos hysteresis input pin ? pull-up resistor valule: approx. 50 k w standby control signal x1 x0 xout standby control signal x1a x0a xout hysteresis inputs r pull-down resistor hysteresis inputs r pull-up resistor hysteresis inputs r
mb90350 series 13 (continued) type circuit remarks f ? cmos level output (i ol = 4 ma, i oh = - 4 ma) ? cmos hysteresis inputs (with the stand- by-time input shutdown function) ? automotive input (with the standby-time input shutdown function) g ? cmos level output (i ol = 4 ma, i oh = - 4 ma) ? cmos hysteresis inputs (with the stand- by-time input shutdown function) ? automotive input (with the standby-time input shutdown function) ? ttl input (with the standby-time input shutdown function) ? programmalble pullup resistor: 50 k w approx. h ? cmos level output (i ol = 3 ma, i oh = - 3 ma) ? cmos hysteresis inputs (with the stand- by-time input shutdown function) ? automotive input (with the standby-time input shutdown function) hysteresis inputs automotive inputs standby control for input shutdown pout nout r pull-up control hysteresis inputs automotive inputs ttl input standby control for input shutdown pout nout r pull-up resistor hysteresis inputs automotive inputs standby control for input shutdown pout nout r
mb90350 series 14 (continued) type circuit remarks i ? cmos level output(i ol = 4 ma) ? cmos hysteresis inputs (with the stand- by-time input shutdown function) ? automotive input (with the standby-time input shutdown function) ? a/d analog input k ? power supply input protection circuit l ? a/d converter reference voltage power supply input pin, with the protection cir- cuit ? flash devices do not have a protection circuit against v cc for pin avrh hysteresis inputs automotive inputs standby control for input shutdown analog input pout nout r ane avr ane
mb90350 series 15 (continued) type circuit remarks n ? cmos level output (i ol = 4 ma, i oh = - 4 ma) ? cmos inputs (with the standby-time input shutdown function) ? automotive input (with the standby-time input shutdown function) ? ttl input (with the standby-time input shutdown function) ? programmable pull-up registor:50 k w approx o ? cmos level output (i ol = 4 ma, i oh = - 4 ma) ? cmos inputs (with the standby-time input shutdown function) ? automotive input (with the standby-time input shutdown function) ? a/d analog input pull-up control cmos inputs automotive inputs ttl input standby control for input shutdown pout nout r pull-up registor cmos inputs automotive inputs standby control for input shutdown analog input pout nout r
mb90350 series 16 n n n n handling devices special care is required for the following when handling the device : ? preventing latch-up ? treatment of unused pins ? using external clock ? precautions for when not using a sub clock signal ? notes on during operation of pll clock mode ? power supply pins (v cc /v ss ) ? pull-up/down resistors ? crystal oscillator circuit ? turning-on sequence of power supply to a/d converter and analog inputs ? connection of unused pins of a/d converter ? notes on energization ? stabilization of power supply voltage ? initialization ? port0 to port3 output during power-on (external-bus mode) ? notes on using can function ? flash security function 1. preventing latch-up cmos ic chips may suffer latch - up under the following conditions : ? a voltage higher than v cc or lower than v ss is applied to an input or output pin. ? a voltage higher than the rated voltage is applied between v cc and v ss . ?the av cc power supply is applied before the v cc voltage. latch-up may increase the power supply current drastically, causing thermal damage to the device. for the same reason, also be careful not to let the analog power-supply voltage (av cc , avrh) exceed the digital power-supply voltage. 2. handling unused pins leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. therefore they must be pulled up or pulled down through resistors. in this case those resistors should be more than 2 k w . unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. 3. using external clock to use external clock, drive the x0 pin and leave x1 pin open. 4. precautions for when not using a sub clock signal if you do not connect pins x0a and x1a to an oscillator, use pull-down handling on the x0a pin, and leave the x1a pin open. x0 x1 mb90350 series open
mb90350 series 17 5. notes on during operation of pll clock mode if the pll clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. performance of this operation, however, cannot be guaranteed. 6. power supply pins (v cc /v ss ) ? if there are multiple v cc and v ss pins, from the point of view of device design, pins to be of the same potential are connected inside of the device to prevent such malfunctioning as latch up. to reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the v cc and v ss pins to the power supply and ground externally. ? connect v cc and v ss to the device from the current supply source at a low impedance. ? as a measure against power supply noise, connect a capacitor of about 0.1 m f as a bypass capacitor between v cc and v ss in the vicinity of v cc and v ss pins of the device 7. pull-up/down resistors the mb90350 series does not support internal pull-up/down resistors (port 0 to port 3: built-in pull-up resistors). use external components where needed. 8. crystal oscillator circuit noises around x0 or x1 pins may be possible causes of abnormal operations. make sure to provide bypass capacitors via shortest distance from x0, x1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits. it is highly recommended to provide a printed circuit board art work surrounding x0 and x1 pins with a ground area for stabilizing the operation. 9. turning-on sequence of power supply to a/d converter and analog inputs make sure to turn on the a/d converter power supply (av cc , avrh) and analog inputs (an0 to an14) after turning-on the digital power supply (v cc ) . turn-off the digital power after turning off the a/d converter supply and analog inputs. in this case, make sure that the voltage does not exceed avrh or av cc (turning on/off the analog and digital power supplies simulta- neously is acceptable). 10. connection of unused pins of a/d converter if a/d converter is used connect unused pins of a/d converter to av cc = v cc , av ss = avrh = v ss . vcc vss vss vcc vss vcc mb90350 series vcc vss vcc vss
mb90350 series 18 11. notes on energization to prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 or more m s (0.2 v to 2.7 v) 12. stabilization of power supply voltage a sudden change in the supply voltage may cause the device to malfunction even within the specified v cc supply voltage operating range. therefore, the v cc supply voltage should be stabilized. for reference, the supply voltage should be controlled so that v cc ripple variations (peak-to-peak value) at commercial frequencies (50 hz to 60 hz) fall below 10 % of the standard v cc supply voltage and the coefficient of fluctuation does not exceed 0.1 v/ms at instantaneous power switching. 13. initialization in the device, there are internal registers which are initialized only by a power-on reset. to initialize these registers, turn on the power again. 14. port 0 to port 3 output during power-on (external-bus mode) as shown below, when power is turned on in external-bus mode, there is a possibility that output signal of port 0 to port 3 might be unstable. 15. notes on using can function to use can function, please set 1 to direct bit of can direct mode register (cdmr). if direct bit is set to 0 (initial value), wait states will be performed when accessing can registers. please refer to hardware manual of mb90350 series for detail of can direct mode register. 16. flash security function the security byte is located in the area of the flash memory. if protection code 01 h is written in the security bit, the flash memory is in the protected state by security. therefore please do not write 01 h in this address if you do not use the security function. please refer to following table for the address of the security bit. flash memory size address for security bit mb90f352 embedded 1 mbit flash memory fe0001 h port0 to port3 port0 to port3 outputs might be unstable port0 to port3 outputs = hi-z v cc 1/2 v cc
mb90350 series 19 n n n n block diagrams ? mb90v340a-101/102 ram 30 k uart prescaler 10-bit adc 15 ch 16-bit reload timer 4 ch io timer 0 clock controller input capture 6 ch output compare 4 ch can controller external interrupt 16lx cpu fmc-16 bus x0,x1 rst sot4 to sot2 sck4 to sck2 sin4 to sin2 avcc avss an14 to an0 avrh adtg tin3, tin1 tot3, tot1 in7 to in4, out7 to out4 rx2 to rx1 tx2 to tx1 int15 to int8 external bus interface ad15 to ad00 a21 to a16 ale rd wrl wrh hrq hak rdy clk x0a,x1a * 3 ch 10-bit dac 1 ch da00 io timer 1 frck0 frck1 8/16-bit ppg 12/8 ch ppgf to ppg8, i 2 c interface sda0 scl0 2 ch 3 ch 1 ch dmac * : mb90v340a-102 (int11r to int9r) ppg6, ppg4, ppg2, ppg0 in1 to in0
mb90350 series 20 ? mb90f352/s, mb90352/s ram rom/flash uart prescaler 10-bit adc 15 ch 16-bit reload timer 4 ch io timer 0 clock controller input capture 6 ch output compare 4 ch can controller external interrupt 16lx cpu fmc-16 bus x0,x1 rst sot3, sot2 sck3, sck2 sin3, sin2 avcc avss an14 to an0 avrh adtg tin3, tin1 tot3, tot1 in7 to in4, out7 to out4 rx1 tx1 int15 to int8 external bus interface ad15 to ad00 a21 to a16 ale rd wrl wrh hrq hak rdy clk x0a,x1a* 128 k 2 ch io timer 1 frck0 frck1 8/16-bit ppg 10/6 ch ppgf to ppg8 1 ch 2 ch i 2 c interface sda0 scl0 1 ch 4 k dmac * : only for devices without s suffix (int11r to int9r) ppg6, ppg4 in1, in0
mb90350 series 21 n n n n memory map note : the high-order portion of bank 00 gives the image of the ff bank rom to make the small model of the c compiler effective. since the low-order 16 bits are the same, the table in rom can be referenced without using the far specification in the pointer declaration. for example, an attempt to access 00c000 h accesses the value at ffc000 h in rom. the rom area in bank ff exceeds 32 kbytes, and its entire image cannot be shown in bank 00. the image between ff8000 h and ffffff h is visible in bank 00, while the image between ff0000 h and ff7fff h is visible only in bank ff. mb90v340a-101/102 ffffff h ff0000 h feffff h fe0000 h fdffff h 00ffff h 008000 h 007fff h 007900 h 0078ff h 000100 h 0000ef h 000000 h ffffff h ff0000 h feffff h fe0000 h fdffff h c00100 h c000ff h 00ffff h 008000 h 007fff h 007900 h 000100 h 0010ff h 001100 h 0000ef h 000000 h mb90f352/s rom (ff bank) rom (fe bank) rom (ff bank) rom (fe bank) external access area rom (image of ff bank) rom (image of ff bank) peripheral peripheral ram 30 k peripheral peripheral ram 4 k : no access external access area mb90352/s
mb90350 series 22 n n n n i/o map (continued) address register abbrevia- tion access resource name initial value 00 h port 0 data register pdr0 r/w port 0 xxxxxxxx 01 h port 1 data register pdr1 r/w port 1 xxxxxxxx 02 h port 2 data register pdr2 r/w port 2 xxxxxxxx 03 h port 3 data register pdr3 r/w port 3 xxxxxxxx 04 h port 4 data register pdr4 r/w port 4 xxxxxxxx 05 h port 5 data register pdr5 r/w port 5 xxxxxxxx 06 h port 6 data register pdr6 r/w port 6 xxxxxxxx 07 h to 0a h reserved 0b h analog input enable register 5 ader5 r/w port 5, a/d 11111111 0c h analog input enable register 6 ader6 r/w port 6, a/d 11111111 0d h reserved 0e h input level select register 0 ilsr0 r/w ports 00000000 0f h input level select register 1 ilsr1 r/w ports 00000000 10 h port 0 direction register ddr0 r/w port 0 00000000 11 h port 1 direction register ddr1 r/w port 1 00000000 12 h port 2 direction register ddr2 r/w port 2 xx000000 13 h port 3 direction register ddr3 r/w port 3 00000000 14 h port 4 direction register ddr4 r/w port 4 xx000000 15 h port 5 direction register ddr5 r/w port 5 xx000000 16 h port 6 direction register ddr6 r/w port 6 00000000 17 h to 19 h reserved 1a h sin input level setting register ddra w uart2, uart3 x00xxxxx 1b h reserved 1c h port 0 pull-up control register pucr0 r/w port 0 00000000 1d h port 1 pull-up control register pucr1 r/w port 1 00000000 1e h port 2 pull-up control register pucr2 r/w port 2 00000000 1f h port 3 pull-up control register pucr3 r/w port 3 00000000 20 h to 37 h reserved 38 h ppg 4 operation mode control register ppgc4 w, r/w 16-bit programable pulse generator 4/5 0x000xx1 39 h ppg 5 operation mode control register ppgc5 w, r/w 0x000001 3a h ppg 45 clock select register ppg45 r/w 000000x0 3b h program address detection control status register 1 pacsr1 r/w address match detection 1 00000000
mb90350 series 23 (continued) address register abbrevia- tion access resource name initial value 3c h ppg 6 operation mode control register ppgc6 w, r/w 16-bit programable pulse generator 6/7 0x000xx1 3d h ppg 7 operation mode control register ppgc7 w, r/w 0x000001 3e h ppg 67 clock select register ppg67 r/w 000000x0 3f h reserved 40 h ppg 8 operation mode control register ppgc8 w, r/w 16-bit programable pulse generator 8/9 0x000xx1 41 h ppg 9 operation mode control register ppgc9 w, r/w 0x000001 42 h ppg 89 clock select register ppg89 r/w 000000x0 43 h reserved 44 h ppg a operation mode control register ppgca w, r/w 16-bit programable pulse generator a/b 0x000xx1 45 h ppg b operation mode control register ppgcb w, r/w 0x000001 46 h ppg ab clock select register ppgab r/w 000000x0 47 h reserved 48 h ppg c operation mode control register ppgcc w,r/w 16-bit programable pulse generator c/d 0x000xx1 49 h ppg d operation mode control register ppgcd w,r/w 0x000001 4a h ppg cd clock select register ppgcd r/w 000000x0 4b h reserved 4c h ppg e operation mode control register ppgce w,r/w 16-bit programable pulse generator e/f 0x000xx1 4d h ppg f operation mode control register ppgcf w,r/w 0x000001 4e h ppg ef clock select register ppgef r/w 000000x0 4f h reserved 50 h input capture control status register 0/1 ics01 r/w input capture 0/1 00000000 51 h input capture edge register 0/1 ice01 r/w, r xxx0x0xx 52 h , 53 h reserved 54 h input capture control status register 4/5 ics45 r/w input capture 4/5 00000000 55 h input capture edge register 4/5 ice45 r xxxxxxxx 56 h input capture control status register 6/7 ics67 r/w input capture 6/7 00000000 57 h input capture edge register 6/7 ice67 r/w, r xxx000xx 58 h to 5b h reserved 5c h output compare control status register 4 ocs4 r/w output compare 4/5 0000xx00 5d h output compare control status register 5 ocs5 r/w 0xx00000
mb90350 series 24 (continued) address register abbrevia- tion access resource name initial value 5e h output compare control status register 6 ocs6 r/w output compare 6/7 0000xx00 5f h output compare control status register 7 ocs7 r/w 0xx00000 60 h timer control status register 0 tmcsr0 r/w 16-bit reload timer 0 00000000 61 h timer control status register 0 tmcsr0 r/w xxxx0000 62 h timer control status register 1 tmcsr1 r/w 16-bit reload timer 1 00000000 63 h timer control status register 1 tmcsr1 r/w xxxx0000 64 h timer control status register 2 tmcsr2 r/w 16-bit reload timer 2 00000000 65 h timer control status register 2 tmcsr2 r/w xxxx0000 66 h timer control status register 3 tmcsr3 r/w 16-bit reload timer 3 00000000 67 h timer control status register 3 tmcsr3 r/w xxxx0000 68 h a/d control status register 0 adcs0 r/w a/d converter 000xxxx0 69 h a/d control status register 1 adcs1 r/w 0000000x 6a h data register 0 adcr0 r 00000000 6b h data register 1 adcr1 r xxxxxx00 6c h a/d setting register 0 adsr0 r/w 00000000 6d h a/d setting register 1 adsr1 r/w 00000000 6e h reserved 6f h rom mirroring register romm w rom mirror xxxxxxx1 70 h to 7f h reserved 80 h to 8f h reserved for can interface 1. refer to n can controllers 90 h to 9a h reserved 9b h dma descriptor channel specification register dcsr r/w dma 00000000 9c h dma status register l dsrl r/w 00000000 9d h dma status register h dsrh r/w 00000000 9e h program address detection control status register 0 pacsr0 r/w address match detection 0 00000000 9f h delayed interrupt/release dirr r/w delayed interrupt 00000000 a0 h low-power mode control register lpmcr w,r/w low power control circuit 00011000 a1 h clock selection register ckscr r,r/w low power control circuit 11111100 a2 h , a3 h reserved a4 h dma stop status register dssr r/w dma 00000000
mb90350 series 25 (continued) address register abbrevia- tion access resource name initial value a5 h automatic ready function selection register arsr w external memory access 0011xx00 a6 h external address output control register hacr w 00000000 a7 h bus control signal selection register ecsr w 0000000x a8 h watchdog timer control register wdtc r,w watchdog timer xxxxx111 a9 h timebase timer control register tbtc w,r/w time base timer 1xx00100 aa h watch timer control register wtc r,r/w watch timer 1x001000 ab h reserved ac h dma enable register l derl r/w dma 00000000 ad h dma enable register h derh r/w 00000000 ae h flash control status register (flash devices only. otherwise reserved) fmcs r,r/w flash memory 000x0000 af h reserved b0 h interrupt control register 00 icr00 w,r/w interrupt control 00000111 b1 h interrupt control register 01 icr01 w,r/w 00000111 b2 h interrupt control register 02 icr02 w,r/w 00000111 b3 h interrupt control register 03 icr03 w,r/w 00000111 b4 h interrupt control register 04 icr04 w,r/w 00000111 b5 h interrupt control register 05 icr05 w,r/w 00000111 b6 h interrupt control register 06 icr06 w,r/w 00000111 b7 h interrupt control register 07 icr07 w,r/w 00000111 b8 h interrupt control register 08 icr08 w,r/w 00000111 b9 h interrupt control register 09 icr09 w,r/w 00000111 ba h interrupt control register 10 icr10 w,r/w 00000111 bb h interrupt control register 11 icr11 w,r/w 00000111 bc h interrupt control register 12 icr12 w,r/w 00000111 bd h interrupt control register 13 icr13 w,r/w 00000111 be h interrupt control register 14 icr14 w,r/w 00000111 bf h interrupt control register 15 icr15 w,r/w 00000111 c0 h to c9 h reserved
mb90350 series 26 (continued) address register abbrevia- tion access resource name initial value ca h external interrupt request enable register 1 enir1 r/w external interrupt 1 00000000 cb h external interrupt request register 1 eirr1 r/w xxxxxxxx cc h external interrupt level register 1 elvr1 r/w 00000000 cd h external interrupt level register 1 elvr1 r/w 00000000 ce h external interrupt source select register eissr r/w 00000000 cf h pll/subclock control register psccr w pll xxxx0000 d0 h dma buffer address pointer l bapl r/w dma xxxxxxxx d1 h dma buffer address pointer m bapm r/w xxxxxxxx d2 h dma buffer address pointer h baph r/w xxxxxxxx d3 h dma control register dmacs r/w xxxxxxxx d4 h i/o register address pointer l ioal r/w xxxxxxxx d5 h i/o register address pointer h ioah r/w xxxxxxxx d6 h data counter l dctl r/w xxxxxxxx d7 h data counter h dcth r/w xxxxxxxx d8 h serial mode register 2 smr2 w,r/w uart2 00000000 d9 h serial control register 2 scr2 w,r/w 00000000 da h reception/transmission data register 2 rdr2/ tdr2 r/w 00000000 db h serial status register 2 ssr2 r,r/w 00001000 dc h extended communication control register 2 eccr2 r,w, r/w 000000xx dd h extended status/control register 2 escr2 r/w 00000100 de h baud rate reload register 20 bgr20 r/w 00000000 df h baud rate reload register 21 bgr21 r/w 00000000 e0 h to ef h reserved f0 h to ff h external 7900 h to 7907 h reserved
mb90350 series 27 (continued) address register abbrevia- tion access resource name initial value 7908 h reload register l4 prll4 r/w 16-bit programable pulse generator 4/5 xxxxxxxx 7909 h reload register h4 prlh4 r/w xxxxxxxx 790a h reload register l5 prll5 r/w xxxxxxxx 790b h reload register h5 prlh5 r/w xxxxxxxx 790c h reload register l6 prll6 r/w 16-bit programable pulse generator 6/7 xxxxxxxx 790d h reload register h6 prlh6 r/w xxxxxxxx 790e h reload register l7 prll7 r/w xxxxxxxx 790f h reload register h7 prlh7 r/w xxxxxxxx 7910 h reload register l8 prll8 r/w 16-bit programable pulse generator 8/9 xxxxxxxx 7911 h reload register h8 prlh8 r/w xxxxxxxx 7912 h reload register l9 prll9 r/w xxxxxxxx 7913 h reload register h9 prlh9 r/w xxxxxxxx 7914 h reload register la prlla r/w 16-bit programable pulse generator a/b xxxxxxxx 7915 h reload register ha prlha r/w xxxxxxxx 7916 h reload register lb prllb r/w xxxxxxxx 7917 h reload register hb prlhb r/w xxxxxxxx 7918 h reload register lc prllc r/w 16-bit programable pulse generator c/d xxxxxxxx 7919 h reload register hc prlhc r/w xxxxxxxx 791a h reload register ld prlld r/w xxxxxxxx 791b h reload register hd prlhd r/w xxxxxxxx 791c h reload register le prlle r/w 16-bit programable pulse generator e/f xxxxxxxx 791d h reload register he prlhe r/w xxxxxxxx 791e h reload register lf prllf r/w xxxxxxxx 791f h reload register hf prlhf r/w xxxxxxxx 7920 h input capture data register 0 ipcp0 r input capture 0/1 xxxxxxxx 7921 h input capture data register 0 ipcp0 r xxxxxxxx 7922 h input capture data register 1 ipcp1 r xxxxxxxx 7923 h input capture data register 1 ipcp1 r xxxxxxxx 7924 h to 7927 h reserved 7928 h input capture data register 4 ipcp4 r input capture 4/5 xxxxxxxx 7929 h input capture data register 4 ipcp4 r xxxxxxxx 792a h input capture data register 5 ipcp5 r xxxxxxxx 792b h input capture data register 5 ipcp5 r xxxxxxxx
mb90350 series 28 (continued) address register abbrevia- tion access resource name initial value 792c h input capture data register 6 ipcp6 r input capture 6/7 xxxxxxxx 792d h input capture data register 6 ipcp6 r xxxxxxxx 792e h input capture data register 7 ipcp7 r xxxxxxxx 792f h input capture data register 7 ipcp7 r xxxxxxxx 7930 h to 7937 h reserved 7938 h output compare register 4 occp4 r/w output compare 4/5 xxxxxxxx 7939 h output compare register 4 occp4 r/w xxxxxxxx 793a h output compare register 5 occp5 r/w xxxxxxxx 793b h output compare register 5 occp5 r/w xxxxxxxx 793c h output compare register 6 occp6 r/w output compare 6/7 xxxxxxxx 793d h output compare register 6 occp6 r/w xxxxxxxx 793e h output compare register 7 occp7 r/w xxxxxxxx 793f h output compare register 7 occp7 r/w xxxxxxxx 7940 h data register 0 tcdt0 r/w i/o timer 0 00000000 7941 h data register 0 tcdt0 r/w 00000000 7942 h control status register 0 tccsl0 r/w 00000000 7943 h control status register 0 tccsh0 r/w 0xxxxxxx 7944 h data register 1 tcdt1 r/w i/o timer 1 00000000 7945 h data register 1 tcdt1 r/w 00000000 7946 h control status register 1 tccsl1 r/w 00000000 7947 h control status register 1 tccsh1 r/w 0xxxxxxx 7948 h timer register 0/reload register 0 tmr0/ tmrlr0 r/w 16-bit reload timer 0 xxxxxxxx 7949 h r/w xxxxxxxx 794a h timer register 1/reload register 1 tmr1/ tmrlr1 r/w 16-bit reload timer 1 xxxxxxxx 794b h r/w xxxxxxxx 794c h timer register 2/reload register 2 tmr2/ tmrlr2 r/w 16-bit reload timer 2 xxxxxxxx 794d h r/w xxxxxxxx 794e h timer register 3/reload register 3 tmr3/ tmrlr3 r/w 16-bit reload timer 3 xxxxxxxx 794f h r/w xxxxxxxx
mb90350 series 29 (continued) address register abbrevia- tion access resource name initial value 7950 h serial mode register 3 smr3 w, r/w uart3 00000000 7951 h serial control register 3 scr3 w, r/w 00000000 7952 h reception/transmission data register 3 rdr3/ tdr3 r/w 00000000 7953 h serial status register 3 ssr3 r,r/w 00001000 7954 h extended communication control reg- ister 3 eccr3 r,w, r/w 000000xx 7955 h extended status/control register 3 escr3 r/w 00000100 7956 h baud rate reload register 30 bgr30 r/w 00000000 7957 h baud rate reload register 31 bgr31 r/w 00000000 7958 h to 796d h reserved 796e h can direct mode register cdmr r/w can clock sync xxxxxxx0 796f h reserved 7970 h i 2 c bus status register 0 ibsr0 r i 2 c interface 0 00000000 7971 h i 2 c bus control register 0 ibcr0 w,r/w 00000000 7972 h i 2 c 10 bit slave address register 0 itbal0 r/w 00000000 7973 h itbah0 r/w 00000000 7974 h i 2 c 10 bit slave address mask register 0 itmkl0 r/w 11111111 7975 h itmkh0 r/w 00111111 7976 h i 2 c 7 bit slave address register 0 isba0 r/w 00000000 7977 h i 2 c 7 bit slave address mask register 0 ismk0 r/w 01111111 7978 h i 2 c data register 0 idar0 r/w 00000000 7979 h , 797a h reserved 797b h i 2 c clock control register 0 iccr0 r/w i 2 c interface 0 00011111 797c h to 79c1 h reserved 79c2 h clock modulator control register cmcr r,r/w clock modulator 0001x000 79c3 h to 79df h reserved
mb90350 series 30 (continued) notes : initial value of x represents unknown value. addresses in the range 0000 h to 00bf h , which are not listed in the table, are reserved for the primary functions of the mcu. a read access to these reserved addresses results reading x and any write access should not be performed. address register abbrevia- tion access resource name initial value 79e0 h program address detection register 0 padr0 r/w address match detection 0 xxxxxxxx 79e1 h program address detection register 0 padr0 r/w xxxxxxxx 79e2 h program address detection register 0 padr0 r/w xxxxxxxx 79e3 h program address detection register 1 padr1 r/w xxxxxxxx 79e4 h program address detection register 1 padr1 r/w xxxxxxxx 79e5 h program address detection register 1 padr1 r/w xxxxxxxx 79e6 h program address detection register 2 padr2 r/w xxxxxxxx 79e7 h program address detection register 2 padr2 r/w xxxxxxxx 79e8 h program address detection register 2 padr2 r/w xxxxxxxx 79e9 h to 79ef h reserved 79f0 h program address detection register 3 padr3 r/w address match detection 1 xxxxxxxx 79f1 h program address detection register 3 padr3 r/w xxxxxxxx 79f2 h program address detection register 3 padr3 r/w xxxxxxxx 79f3 h program address detection register 4 padr4 r/w xxxxxxxx 79f4 h program address detection register 4 padr4 r/w xxxxxxxx 79f5 h program address detection register 4 padr4 r/w xxxxxxxx 79f6 h program address detection register 5 padr5 r/w xxxxxxxx 79f7 h program address detection register 5 padr5 r/w xxxxxxxx 79f8 h program address detection register 5 padr5 r/w xxxxxxxx 79f9 h to 7bff h reserved 7c00 h to 7cff h reserved for can interface 1. refer to n can controllers 7d00 h to 7dff h reserved for can interface 1. refer to n can controllers 7e00 h to 7fff h reserved
mb90350 series 31 n n n n can controllers the can controller has the following features : ? conforms to can specification version 2.0 part a and b supports transmission/reception in standard frame and extended frame formats ? supports transmitting of data frames by receiving remote frames ? 16 transmitting/receiving message buffers 29-bit id and 8-byte data multi-level message buffer configuration ? provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as id acceptance mask two acceptance mask registers in either standard frame format or extended frame formats ? bit rate programmable from 10 kbits/s to 2 mbits/s (when input clock is at 16 mhz) list of control registers (1) address register abbreviation access initial value can1 000080 h message buffer enable register bvalr r/w 00000000 00000000 000081 h 000082 h transmit request register treqr r/w 00000000 00000000 000083 h 000084 h transmit cancel register tcanr w 00000000 00000000 000085 h 000086 h transmission complete register tcr r/w 00000000 00000000 000087 h 000088 h receive complete register rcr r/w 00000000 00000000 000089 h 00008a h remote request receiving register rrtrr r/w 00000000 00000000 00008b h 00008c h receive overrun register rovrr r/w 00000000 00000000 00008d h 00008e h reception interrupt enable register rier r/w 00000000 00000000 00008f h
mb90350 series 32 list of control registers (2) address register abbreviation access initial value can1 007d00 h control status register csr r/w, w r/w, r 0xxxx0x1 00xxx000 007d01 h 007d02 h last event indicator register leir r/w 000x0000 xxxxxxxx 007d03 h 007d04 h receive/transmit error counter rtec r 00000000 00000000 007d05 h 007d06 h bit timing register btr r/w 11111111 x1111111 007d07 h 007d08 h ide register ider r/w xxxxxxxx xxxxxxxx 007d09 h 007d0a h transmit rtr register trtrr r/w 00000000 00000000 007d0b h 007d0c h remote frame receive waiting register rfwtr r/w xxxxxxxx xxxxxxxx 007d0d h 007d0e h transmit interrupt enable register tier r/w 00000000 00000000 007d0f h 007d10 h acceptance mask select register amsr r/w xxxxxxxx xxxxxxxx 007d11 h 007d12 h xxxxxxxx xxxxxxxx 007d13 h 007d14 h acceptance mask register 0 amr0 r/w xxxxxxxx xxxxxxxx 007d15 h 007d16 h xxxxxxxx xxxxxxxx 007d17 h 007d18 h acceptance mask register 1 amr1 r/w xxxxxxxx xxxxxxxx 007d19 h 007d1a h xxxxxxxx xxxxxxxx 007d1b h
mb90350 series 33 list of message buffers (id registers) (1) address register abbreviation access initial value can1 007c00 h to 007c1f h general-purpose ram ? r/w xxxxxxxx to xxxxxxxx 007c20 h id register 0 idr0 r/w xxxxxxxx xxxxxxxx 007c21 h 007c22 h xxxxxxxx xxxxxxxx 007c23 h 007c24 h id register 1 idr1 r/w xxxxxxxx xxxxxxxx 007c25 h 007c26 h xxxxxxxx xxxxxxxx 007c27 h 007c28 h id register 2 idr2 r/w xxxxxxxx xxxxxxxx 007c29 h 007c2a h xxxxxxxx xxxxxxxx 007c2b h 007c2c h id register 3 idr3 r/w xxxxxxxx xxxxxxxx 007c2d h 007c2e h xxxxxxxx xxxxxxxx 007c2f h 007c30 h id register 4 idr4 r/w xxxxxxxx xxxxxxxx 007c31 h 007c32 h xxxxxxxx xxxxxxxx 007c33 h 007c34 h id register 5 idr5 r/w xxxxxxxx xxxxxxxx 007c35 h 007c36 h xxxxxxxx xxxxxxxx 007c37 h 007c38 h id register 6 idr6 r/w xxxxxxxx xxxxxxxx 007c39 h 007c3a h xxxxxxxx xxxxxxxx 007c3b h 007c3c h id register 7 idr7 r/w xxxxxxxx xxxxxxxx 007c3d h 007c3e h xxxxxxxx xxxxxxxx 007c3f h
mb90350 series 34 list of message buffers (id registers) (2) address register abbreviation access initial value can1 007c40 h id register 8 idr8 r/w xxxxxxxx xxxxxxxx 007c41 h 007c42 h xxxxxxxx xxxxxxxx 007c43 h 007c44 h id register 9 idr9 r/w xxxxxxxx xxxxxxxx 007c45 h 007c46 h xxxxxxxx xxxxxxxx 007c47 h 007c48 h id register 10 idr10 r/w xxxxxxxx xxxxxxxx 007c49 h 007c4a h xxxxxxxx xxxxxxxx 007c4b h 007c4c h id register 11 idr11 r/w xxxxxxxx xxxxxxxx 007c4d h 007c4e h xxxxxxxx xxxxxxxx 007c4f h 007c50 h id register 12 idr12 r/w xxxxxxxx xxxxxxxx 007c51 h 007c52 h xxxxxxxx xxxxxxxx 007c53 h 007c54 h id register 13 idr13 r/w xxxxxxxx xxxxxxxx 007c55 h 007c56 h xxxxxxxx xxxxxxxx 007c57 h 007c58 h id register 14 idr14 r/w xxxxxxxx xxxxxxxx 007c59 h 007c5a h xxxxxxxx xxxxxxxx 007c5b h 007c5c h id register 15 idr15 r/w xxxxxxxx xxxxxxxx 007c5d h 007c5e h xxxxxxxx xxxxxxxx 007c5f h
mb90350 series 35 list of message buffers (dlc registers and data registers) (1) address register abbreviation access initial value can1 007c60 h dlc register 0 dlcr0 r/w xxxxxxxx 007c61 h 007c62 h dlc register 1 dlcr1 r/w xxxxxxxx 007c63 h 007c64 h dlc register 2 dlcr2 r/w xxxxxxxx 007c65 h 007c66 h dlc register 3 dlcr3 r/w xxxxxxxx 007c67 h 007c68 h dlc register 4 dlcr4 r/w xxxxxxxx 007c69 h 007c6a h dlc register 5 dlcr5 r/w xxxxxxxx 007c6b h 007c6c h dlc register 6 dlcr6 r/w xxxxxxxx 007c6d h 007c6e h dlc register 7 dlcr7 r/w xxxxxxxx 007c6f h 007c70 h dlc register 8 dlcr8 r/w xxxxxxxx 007c71 h 007c72 h dlc register 9 dlcr9 r/w xxxxxxxx 007c73 h 007c74 h dlc register 10 dlcr10 r/w xxxxxxxx 007c75 h 007c76 h dlc register 11 dlcr11 r/w xxxxxxxx 007c77 h 007c78 h dlc register 12 dlcr12 r/w xxxxxxxx 007c79 h 007c7a h dlc register 13 dlcr13 r/w xxxxxxxx 007c7b h 007c7c h dlc register 14 dlcr14 r/w xxxxxxxx 007c7d h 007c7e h dlc register 15 dlcr15 r/w xxxxxxxx 007c7f h
mb90350 series 36 list of message buffers (dlc registers and data registers) (2) address register abbreviation access initial value can1 007c80 h to 007c87 h data register 0 (8 bytes) dtr0 r/w xxxxxxxx to xxxxxxxx 007c88 h to 007c8f h data register 1 (8 bytes) dtr1 r/w xxxxxxxx to xxxxxxxx 007c90 h to 007c97 h data register 2 (8 bytes) dtr2 r/w xxxxxxxx to xxxxxxxx 007c98 h to 007c9f h data register 3 (8 bytes) dtr3 r/w xxxxxxxx to xxxxxxxx 007ca0 h to 007ca7 h data register 4 (8 bytes) dtr4 r/w xxxxxxxx to xxxxxxxx 007ca8 h to 007caf h data register 5 (8 bytes) dtr5 r/w xxxxxxxx to xxxxxxxx 007cb0 h to 007cb7 h data register 6 (8 bytes) dtr6 r/w xxxxxxxx to xxxxxxxx 007cb8 h to 007cbf h data register 7 (8 bytes) dtr7 r/w xxxxxxxx to xxxxxxxx 007cc0 h to 007cc7 h data register 8 (8 bytes) dtr8 r/w xxxxxxxx to xxxxxxxx 007cc8 h to 007ccf h data register 9 (8 bytes) dtr9 r/w xxxxxxxx to xxxxxxxx 007cd0 h to 007cd7 h data register 10 (8 bytes) dtr10 r/w xxxxxxxx to xxxxxxxx 007cd8 h to 007cdf h data register 11 (8 bytes) dtr11 r/w xxxxxxxx to xxxxxxxx 007ce0 h to 007ce7 h data register 12 (8 bytes) dtr12 r/w xxxxxxxx to xxxxxxxx 007ce8 h to 007cef h data register 13 (8 bytes) dtr13 r/w xxxxxxxx to xxxxxxxx
mb90350 series 37 list of message buffers (dlc registers and data registers) (3) address register abbreviation access initial value can1 007cf0 h to 007cf7 h data register 14 (8 bytes) dtr14 r/w xxxxxxxx to xxxxxxxx 007cf8 h to 007cff h data register 15 (8 bytes) dtr15 r/w xxxxxxxx to xxxxxxxx
mb90350 series 38 n n n n interrupt factors, interrupt vectors, interrupt control register (continued) interrupt cause ei 2 os clear dma ch number interrupt vector interrupt control register number address number address reset n ? #08 ffffdc h ?? int9 instruction n ? #09 ffffd8 h ?? exception n ? #10 ffffd4 h ?? reserved n ? #11 ffffd0 h icr00 0000b0 h reserved n ? #12 ffffcc h can 1 rx / input capture 6 y1 ? #13 ffffc8 h icr01 0000b1 h can 1 tx/ns / input capture 7 y1 ? #14 ffffc4 h i 2 cn ? #15 ffffc0 h icr02 0000b2 h reserved n ? #16 ffffbc h 16-bit reload timer 0 y1 0 #17 ffffb8 h icr03 0000b3 h 16-bit reload timer 1 y1 1 #18 ffffb4 h 16-bit reload timer 2 y1 2 #19 ffffb0 h icr04 0000b4 h 16-bit reload timer 3 y1 ? #20 ffffac h ppg 4/5 n ? #21 ffffa8 h icr05 0000b5 h ppg 6/7 n ? #22 ffffa4 h ppg 8/9/c/d n ? #23 ffffa0 h icr06 0000b6 h ppg a/b/e/f n ? #24 ffff9c h time base timer n ? #25 ffff98 h icr07 0000b7 h external interrupt 8 to 11 y1 3 #26 ffff94 h watch timer n ? #27 ffff90 h icr08 0000b8 h external interrupt 12 to 15 y1 4 #28 ffff8c h a/d converter y1 5 #29 ffff88 h icr09 0000b9 h i/o timer 0 / i/o timer 1 n ? #30 ffff84 h input capture 4/5 y1 6 #31 ffff80 h icr10 0000ba h output compare 4/5 y1 7 #32 ffff7c h input capture 0/1 y1 8 #33 ffff78 h icr11 0000bb h output compare 6/7 y1 9 #34 ffff74 h reserved n 10 #35 ffff70 h icr12 0000bc h reserved n 11 #36 ffff6c h uart 3 rx y2 12 #37 ffff68 h icr13 0000bd h uart 3 tx y1 13 #38 ffff64 h
mb90350 series 39 (continued) y1 : usable y2 : usable, with ei 2 os stop function n : unusable notes : the peripheral resources sharing the icr register have the same interrupt level. when two peripheral resources share the icr register, only one can use extended intelligent i/o service at a time. when either of the two peripheral resources sharing the icr register specifies extended intelligent i/o service, the other one cannot use interrupts. interrupt cause ei 2 os clear dma ch number interrupt vector interrupt control register number address number address uart 2 rx y2 14 #39 ffff60 h icr14 0000be h uart 2 tx y1 15 #40 ffff5c h flash memory n ? #41 ffff58 h icr15 0000bf h delayed interrupt n ? #42 ffff54 h
mb90350 series 40 n n n n electrical characteristics 1. absolute maximum ratings (v ss = av ss = 0 v) (continued) parameter symbol rating unit remarks min max power supply voltage v cc v ss - 0.3 v ss + 6.0 v av cc v ss - 0.3 v ss + 6.0 v v cc = av cc * 1 avrh v ss - 0.3 v ss + 6.0 v av cc 3 avrh* 1 input voltage v i v ss - 0.3 v ss + 6.0 v *2 output voltage v o v ss - 0.3 v ss + 6.0 v *2 maximum clamp current i clamp - 4.0 + 4.0 ma *4 total maximum clamp current s |i clamp | ? 40 ma *4 l level maximum output current i ol ? 15 ma *3 l level average output current i olav ? 4ma*3 l level maximum overall output current s i ol ? 100 ma *3 l level average overall output current s i olav ? 50 ma *3 h level maximum output current i oh ?- 15 ma *3 h level average output current i ohav ?- 4ma*3 h level maximum overall output current s i oh ?- 100 ma *3 h level average overall output current s i ohav ?- 50 ma *3 power consumption p d ? 240 mw + 105 c < t a + 125 c, normal operation : maximum frequency 16 mhz ? 320 mw - 40 c < t a + 105 c, normal operation : maximum frequency 24 mhz operating temperature t a - 40 + 105 c - 40 + 125 c*5 storage temperature t stg - 55 + 150 c
mb90350 series 41 (continued) *1: set av cc and v cc to the same voltage. make sure that av cc does not exceed v cc and that the voltage at the analog inputs does not exceed av cc when the power is switched on. *2: v i and v o should not exceed v cc + 0.3 v. v i should not exceed the specified ratings. however if the maximun current to/from an input is limited by some means with external components, the i clamp rating supercedes the v i rating. *3: applicable to pins: p00 to p07, p10 to p17, p20 to p25, p30 to p37, p40 to p45, p50 to p56, p60 to p67 *4: applicable to pins: p00 to p07, p10 to p17, p20 to p25, p30 to p37, p40 to p45, p50 to p56 (for evaluation : p50 to p55) , p60 to p67 use within recommended operating conditions. use at dc voltage (current) the + b signal should always be applied a limiting resistance placed between the + b signal and the microcontroller. the value of the limiting resistance should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective diode and increase the potential at the v cc pin, and this may affect other devices. note that if a + b signal is input when the microcontroller power supply is off (not fixed at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. note that if the + b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. care must be taken not to leave the + b input pin open. sample recommended circuits: *5 : if used exceeding t a = + 105 c, be sure to contact fujitsu for reliability limitations. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. p-ch n-ch v cc r ? input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode
mb90350 series 42 2. recommended conditions (v ss = av ss = 0 v) * : if used exceeding t a = + 105 c, be sure to contact fujitsu for reliability limitations. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v cc , av cc 4.0 5.0 5.5 v under normal operation 3.5 5.0 5.5 v under normal operation, when not using the a/d converter and not flash programming. 4.5 5.0 5.5 v when external bus is used. 3.0 ? 5.5 v maintains ram data in stop mode smooth capacitor c s 0.1 ? 1.0 m f use a ceramic capacitor or capacitor of bet- ter ac characteristics. capacitor at the v cc should be greater than this capacitor. operating temperature t a - 40 ?+ 105 c - 40 ?+ 125 c* c c s c pin connection diagram 24 16 - 40 105 125 operation guaranteed range operation temperature t a ( c) internal clock f cp (mhz)
mb90350 series 43 3. dc characteristics (t a = - 40 c to + 105 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) (t a = - 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 16 mhz, v ss = av ss = 0 v) (continued) parameter sym- bol pin condition value unit remarks min typ max input h voltage (at v cc = 5 v 10 % ) v ihs ?? 0.8 v cc ? v cc + 0.3 v port inputs if cmos hysteresis input levels are selected (except p12, p15, p44, p45, p50) v iha ?? 0.8 v cc ? v cc + 0.3 v port inputs if automotive input levels are selected v iht ?? 2.0 ? v cc + 0.3 v port inputs if ttl input levels are selected v ihs ?? 0.7 v cc ? v cc + 0.3 v p12, p15, p50 inputs if cmos input levels are selected v ihi ?? 0.7 v cc ? v cc + 0.3 v p44, p45 inputs if cmos hysteresis input levels are selected v ihr ?? 0.8 v cc ? v cc + 0.3 v rst input pin (cmos hysteresis) v ihm ?? v cc - 0.3 ? v cc + 0.3 v md input pin input l voltage (at v cc = 5 v 10 % ) v ils ?? v ss - 0.3 ? 0.2 v cc v port inputs if cmos hysteresis input levels are selected (except p12, p15, p44, p45, p50) v ila ?? v ss - 0.3 ? 0.5 v cc v port inputs if automotive input levels are selected v ilt ?? v ss - 0.3 ? 0.8 v port inputs if ttl input levels are selected v ils ?? v ss - 0.3 ? 0.3 v cc v p12, p15, p50 inputs if cmos input levels are selected v ili ?? v ss - 0.3 ? 0.3 v cc v p44, p45 inputs if cmos hysteresis input levels are selected v ilr ?? v ss - 0.3 ? 0.2 v cc v rst input pin (cmos hysteresis) v ilm ?? v ss - 0.3 ? v ss + 0.3 v md input pin output h voltage v oh normal outputs v cc = 4.5 v, i oh = - 4.0 ma v cc - 0.5 ?? v output h voltage v ohi i 2 c current outputs v cc = 4.5 v, i oh = - 3.0 ma v cc - 0.5 ?? v output l voltage v ol normal outputs v cc = 4.5 v, i ol = 4.0 ma ?? 0.4 v output l voltage v oli i 2 c current outputs v cc = 4.5 v, i ol = 3.0 ma ?? 0.4 v
mb90350 series 44 (continued) (t a = - 40 c to + 105 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) (t a = - 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 16 mhz, v ss = av ss = 0 v) * : the power supply current is measured with an external clock. parameter sym- bol pin condition value unit remarks min typ max input leak current i il ? v cc = 5.5 v, v ss < v i < v cc - 1 ? 1 m a pull-up resistance r up p00 to p07, p10 to p17, p20 to p25, p30 to p37, rst ? 25 50 100 k w pull-down resistance r down md2 ? 25 50 100 k w except flash devices power supply current* i cc v cc v cc = 5.0 v, internal frequency : 24 mhz, at normal operation. ? 50 65 ma mb90f352 v cc = 5.0 v, internal frequency : 24 mhz, at writing flash memory. ? 65 80 ma mb90f352 v cc = 5.0 v, internal frequency : 24 mhz, at erasing flash memory. ? 70 85 ma mb90f352 i ccs v cc = 5.0 v, internal frequency : 24 mhz, at sleep mode. ? 25 35 ma mb90f352 i cts v cc = 5.0 v, internal frequency : 2 mhz, at main timer mode ? 0.3 0.8 ma mb90f352 i ctspll6 v cc = 5.0 v, internal frequency : 24 mhz, at pll timer mode, external frequency = 4 mhz ? 4 7 ma mb90f352 i ccl v cc = 5.0 v, internal frequency: 8 khz, at sub operation t a = + 25 c ? 170 360 m a mb90f352 i ccls v cc = 5.0 v, internal frequency: 8 khz, at sub sleep t a = + 25 c ? 20 50 m a mb90f352 i cct v cc = 5.0 v, internal frequency: 8 khz, at watch mode t a = + 25 c ? 10 35 m a mb90f352 i cch v cc = 5.0 v, at stop mode, t a = + 25 c ? 725 m a mb90f352 input capacity c in other than c, av cc , av ss , avrh, v cc , v ss , ?? 515pf
mb90350 series 45 4. ac characteristics (1) clock timing (t a = - 40 c to + 105 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) (t a = - 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 16 mhz, v ss = av ss = 0 v) * : when selecting the pll clock, the range of clock frequency is limited. use this product within range as mentioned in relation among external clock frequency and machine clock frequency. parameter symbol pin value unit remarks min typ max clock frequency f c x0, x1 3 ? 16 mhz when using an oscillation circuit x0 3 ? 24 mhz when using an external clock* f cl x0a, x1a 32.768 100 khz clock cycle time t cyl x0, x1 62.5 ? 333 ns when using an oscillation circuit x0 41.67 ? 333 ns when using an external clock t cyll x0a, x1a 10 30.5 m s input clock pulse width p wh , p wl x0 10 ?? ns duty ratio is about 30 % to 70 % . p whl , p wll x0a 5 15.2 ?m s input clock rise and fall time t cr , t cf x0 ?? 5 ns when using external clock internal operating clock frequency (machine clock) f cp ? 1.5 ? 24 mhz when using main clock at t a + 105 c 16 when using main clock at t a + 125 c f cpl ? 8.192 50 khz when using sub clock internal operating clock cycle time (machine clock) t cp ? 41.67 ? 666 ns when using main clock at t a + 105 c 62.5 when using main clock at t a + 125 c t cpl ? 20 122.1 ?m s when using sub clock x0 t cyl t cf t cr 0.8 v cc 0.2 v cc p wh p wl x0a t cyll t cf t cr 0.8 v cc 0.2 v cc p whl p wll clock timing
mb90350 series 46 guaranteed operation range of mb90350 series * : when using the oscillation circuit, the maximum oscillation clock frequency is 16 mhz external clock frequency and machine clock frequency 24 5.5 3.5 1.5 4 power supply voltage v cc (v) guaranteed operation range guaranteed pll operation range 4.0 guaranteed a/d converter operation range machine clock f cp (mhz) 24 4.0 16 12 3 4 12 24 internal clock f cp (mhz) external clock f c (mhz) * x 4 x 3 x 2 x 1 x 1/2 (pll off) 8 8 guaranteed oscillation frequency range 1.5 16 x 6
mb90350 series 47 (2) reset standby input (t a = - 40 c to + 105 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) (t a = - 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 16 mhz, v ss = av ss = 0 v) * : oscillation time of oscillator is the time that the amplitude reaches 90 % . in the crystal oscillator, the oscillation time is between several ms to tens of ms. in far / ceramic oscillators, the oscillation time is between hundreds of m s to several ms. with an external clock, the oscillation time is 0 ms. parameter symbol pin value unit remarks min max reset input time t rstl rst 500 ? ns under normal operation oscillation time of oscillator* + 100 m s ?m s in stop mode, sub clock mode, sub sleep mode and watch mode 100 ?m s in main timer mode and pll timer mode t rstl 0.2 v cc 0.2 v cc rst x0 90% of amplitude instruction execution oscillation stabilization waiting time oscillation time of oscillator internal operation clock internal reset 100 m s 0.2 v cc rst t rstl 0.2 v cc under normal operation: in stop mode, sub clock mode, sub sleep mode, watch mode:
mb90350 series 48 (3) power on reset (t a = - 40 c to + 105 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) (t a = - 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 16 mhz, v ss = av ss = 0 v) (4) clock output timing (t a = - 40 c to + 105 c, v cc = 5.0 v 10 % , v ss = 0.0 v, f cp 24 mhz) parameter symbol pin condition value unit remarks min max power on rise time t r v cc ? 0.05 30 ms power off time t off v cc 1 ? ms due to repetitive operation parameter symbol pin condition value unit remarks min max cycle time t cyc clk ? 62.5 ? ns f cp = 16 mhz 41.76 ? ns f cp = 24 mhz clk - ? clk t chcl clk ? 20 ? ns f cp = 16 mhz 13 ? ns f cp = 24 mhz v cc v cc v ss 3 v t r t off 2.7 v 0.2 v 0.2 v 0.2 v holds ram data if you change the power supply voltage too rapidly, a power on reset may occur. we recommend that you startup smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. perform while not using the pll clock. however, if voltage drops are within 1 v/s, you can operate while using the pll clock. we recommend a rise of 50 mv/ms maximum. clk 2.4 v t cyc 2.4 v 0.8 v t chcl
mb90350 series 49 (5) bus timing (read) (t a = C40 c to +105 c, v cc = 5.0 v 10 % , v ss = 0.0 v, f cp 24 mhz) parameter sym- bol pin condition value unit remarks min max ale pulse width t lhll ale ? t cp /2 - 10 ? ns valid address t ale time t avll ale, a21 to a16, ad15 to ad00 t cp /2 - 20 ? ns ale t address valid time t llax ale, ad15 to ad00 t cp /2 - 15 ? ns valid address t rd time t avrl a21 toa16, ad15 to ad00, rd t cp - 15 ? ns valid address t valid data input t avdv a21 to a16, ad15 to ad00 ? 5 t cp /2 - 60 ns rd pulse width t rlrh rd 3 t cp /2 - 20 ? ns rd t valid data input t rldv rd , ad15 to ad00 ? 3 t cp /2 - 50 ns rd - t data hold time t rhdx rd , ad15 to ad00 0 ? ns rd t ale - time t rhlh rd , ale t cp /2 - 15 ? ns rd - t address valid time t rhax rd , a21 to a16 t cp /2 - 10 ? ns valid address t clk - time t avch a21 to a16, ad15 to ad00, clk t cp /2 - 16 ? ns rd t clk - time t rlch rd , clk t cp /2 - 15 ? ns ale t rd time t llrl ale, rd t cp /2 - 15 ? ns
mb90350 series 50 a21 to a16 0.8 v 2.4 v 2.4 v 0.8 v t rhax ad15 to ad00 0.8 v 2.4 v 2.4 v 0.8 v address vil vih vih vil read data t rhdx t rldv t avdv clk t avch 2.4 v t rlch 2.4 v ale 2.4 v t lhll 2.4 v t rhlh 0.8 v t llax 2.4 v t avll rd t llrl t rlrh 0.8 v 2.4 v t avrl
mb90350 series 51 (6) bus timing (write) (t a = C40 c to +105 c, v cc = 5.0 v 10 % , v ss = 0.0 v, f cp 24 mhz) parameter symbol pin condition value unit remarks min max valid address t wr time t avwl a21 to a16, ad15 to ad00, wr ? t cp - 15 ? ns wr pulse width t wlwh wr 3 t cp /2 - 20 ? ns valid data output t wr - time t dvwh ad15 to ad00, wr 3 t cp /2 - 20 ? ns wr - t data hold time t whdx ad15 to ad00, wr 15 ? ns wr - t address valid time t whax a21 to a16, wr t cp /2 - 10 ? ns wr - t ale - time t whlh wr , ale t cp /2 - 15 ? ns wr t clk - time t wlch wr , clk t cp /2 - 15 ? ns clk t wlch 2.4 v ale t whlh 2.4 v wr (wrl, wrh) t wlwh 0.8 v 2.4 v t avwl a21 to a16 0.8 v 2.4 v 2.4 v 0.8 v t whax ad15 to ad00 2.4 v 0.8 v address 0.8 v 2.4 v write data t dvwh 0.8 v 2.4 v t whdx
mb90350 series 52 (7) ready input timing (t a = C40 c to +105 c, v cc = 5.0 v 10 % , v ss = 0.0 v, f cp 24 mhz) note : if the rdy setup time is insufficient, use the auto-ready function. parameter sym- bol pin test condition rated value units remarks min max rdy setup time t ryhs rdy ? 45 ? ns f cp = 16 mhz 32 ? ns f cp = 24 mhz rdy hold time t ryhh rdy 0 ? ns clk 2.4 v ale rd/wr rdy when wait is not used. v ih v ih t ryhh rdy when wait is used. t ryhs v il
mb90350 series 53 (8) hold timing (t a = C40 c to +105 c, v cc = 5.0 v 10 % , v ss = 0.0 v, f cp 24 mhz) note : there is more than 1 cycle from when hrq reads in until the hak is changed. parameter symbol pin condition value units remarks min max pin floating t hak time t xhal hak ? 30 t cp ns hak - time t pin valid time t hahv hak t cp 2 t cp ns hak each pin high-z t hahv t xhal 2.4v 0.8v 2.4v 2.4v 0.8v 0.8v
mb90350 series 54 (9) uart 2/3 (t a = C40 c to +105 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = 0.0 v) (t a = C40 c to +125 c, v cc = 5.0 v 10 % , f cp 16 mhz, v ss = 0.0 v) * : refer to (1) clock timing rating for t cp (internal operating clock cycle time). notes : ac characteristic in clk synchronized mode. c l is load capacity value of pins when testing. t cp is the machine cycle (unit : ns) parameter symbol pin condition value unit remarks min max serial clock cycle time t scyc sck2, sck3 internal clock operation output pins are c l = 80 pf + 1 ttl 8 t cp * ? ns sck ? sot delay time t slov sck2, sck3, sot2, sot3 - 80 + 80 ns valid sin ? sck - t ivsh sck2, sck3, sin0 to sin4 100 ? ns sck - ? valid sin hold time t shix sck2, sck3, sin2, sin3 60 ? ns serial clock h pulse width t shsl sck2, sck3 external clock operation output pins are c l = 80 pf + 1 ttl 4 t cp * ? ns serial clock l pulse width t slsh sck2, sck3 4 t cp * ? ns sck ? sot delay time t slov sck2, sck3, sot2, sot3 ? 150 ns valid sin ? sck - t ivsh sck2, sck3, sin2, sin3 60 ? ns sck - ? valid sin hold time t shix sck2, sck3, sin2, sin3 60 ? ns internal shift clock mode sck 2.4 v t scyc 0.8 v sot 0.8 v 2.4 v 0.8 v t slov sin v il v ih t ivsh v il v ih t shix
mb90350 series 55 (10) trigger input timing (t a = C40 c to +105 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = 0.0 v) (t a = C40 c to +125 c, v cc = 5.0 v 10 % , f cp 16 mhz, v ss = 0.0 v) parameter symbol pin condition value unit remarks min max input pulse width t trgh t trgl int8 to int15, int9r to int11r, adtg ? 5 t cp ? ns external shift clock mode sck v ih t slsh v il sot 0.8 v 2.4 v t slov sin v il v ih t ivsh v il v ih t shix v ih v il t shsl v il v ih t trgh v il v ih t trgl int8 to int15, int9r to int11r, adtg
mb90350 series 56 (11) timer related resource input timing (t a = C40 c to +105 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = 0.0 v) (t a = C40 c to +125 c, v cc = 5.0 v 10 % , f cp 16 mhz, v ss = 0.0 v) (12) timer related resource output timing (t a = C40 c to +105 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = 0.0 v) (t a = C40 c to +125 c, v cc = 5.0 v 10 % , f cp 16 mhz, v ss = 0.0 v) parameter symbol pin condition value unit remarks min max input pulse width t tiwh tin1, tin3, in0, in1, in4 to in7 ? 4 t cp ? ns t tiwl parameter symbol pin condition value unit remarks min max clk - t t out change time t to tot1, tot3, ppg4, ppg6, ppg8 to ppgf ? 30 ? ns v il v ih t tiwh v il v ih t tiwl tin1, tin3, in0, in1, in4 to in7 clk 2.4 v 0.8 v 2.4 v t to tot1, tot3, ppg4, ppg6 ppg8 to ppgf
mb90350 series 57 (13) i 2 c timing (t a = C40 c to +105 c, v cc = av cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0.0 v) (t a = C40 c to +125 c, v cc = av cc = 5.0 v 10 % , f cp 16 mhz, v ss = av ss = 0.0 v) *1 : r,c : pull-up resistor and load capacitor of the scl and sda lines. *2 : the maximum t hddat have only to be met if the device does not stretch the l width (t low ) of the scl signal. *3 : a fast-mode i 2 c -bus device can be used in a standard-mode i 2 c-bus system, but the requirement t sudat 3 250 ns must then be met. *4 : for use at over 100 khz, set the machine clock to at least 6 mhz. parameter symbol condition standard-mode fast-mode* 4 unit min max min max scl clock frequency f scl r = 1.7 k w , c = 50 pf* 1 0 100 0 400 khz hold time (repeated) start condition sda ? scl t hdsta 4.0 ? 0.6 ?m s l width of the scl clock t low 4.7 ? 1.3 ?m s h width of the scl clock t high 4.0 ? 0.6 ?m s set-up time for a repeated start condition scl -? sda t susta 4.7 ? 0.6 ?m s data hold time scl ? sda - t hddat 0 3.45* 2 00.9* 3 m s data set-up time sda -? scl - t sudat 250 ? 100 ? ns set-up time for stop condition scl -? sda - t susto 4.0 ? 0.6 ?m s bus free time between a stop and start condition t bus 4.7 ? 1.3 ?m s sda scl t low t sudat t hdsta t bus t hdsta t hddat t high t susta t susto
mb90350 series 58 5. a/d converter (t a = - 40 c to + 105 c, 3.0 v avrh, v cc = av cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) (t a = - 40 c to + 125 c, 3.0 v avrh, v cc = av cc = 5.0 v 10 % , f cp 16 mhz, v ss = av ss = 0 v) * : if a/d convertor is not operating, a current when cpu is stopped is applicable (v cc = av cc = avrh = 5.0 v) . note : the accuracy gets worse as | avrh - av ss | becomes smaller. parameter symbol pin value unit remarks min typ max resolution ?? ? ? 10 bit total error ?? ? ? 3.0 lsb nonlinearity error ?? ? ? 2.5 lsb differential nonlinearity error ?? ? ? 1.9 lsb zero reading voltage v ot an0 to an14 av ss - 1.5 av ss + 0.5 av ss + 2.5 lsb full scale reading voltage v fst an0 to an14 avrh - 3.5 avrh - 1.5 avrh + 0.5 lsb compare time ?? 1.0 ? 16,500 m s 4.5 v av cc 5.5 v 2.0 4.0 v av cc < 4.5 v sampling time ?? 0.5 ? m s 4.5 v av cc 5.5 v 1.2 4.0 v av cc < 4.5 v analog port input current i ain an0 to an14 - 0.3 ? +0.3 m a analog input voltage range v ain an0 to an14 av ss ? avrh v reference voltage range ? avrh av ss + 2.7 ? av cc v power supply current i a av cc ? 3.5 7.5 ma i ah av cc ?? 5 m a* reference voltage current i r avrh ? 600 900 m a i rh avrh ?? 5 m a* offset between input channels ? an0 to an14 ?? 4lsb
mb90350 series 59 6. definition of a/d converter terms (continued) resolution : analog variation that is recognized by an a/d converter. non linearity error : deviation between a line across zero-transition line ( 00 0000 0000 ? ? 00 0000 0001 ) and full-scale transition line ( 11 1111 1110 ? ? 11 1111 1111 ) and actual conversion characteristics. differential linearity error : deviation of input voltage, which is required for changing output code by 1 lsb, from an ideal value. total error : difference between an actual value and an ideal value. a total error includes zero transition error, full-scale transition error, and linear error. zero reading voltage : input voltage which results in the minimum conversion value. full scale reading voltage : input voltage which results in the maximum conversion value. 3ff 3fe 3fd 004 003 002 001 av ss avrh v nt 1.5 lsb 0.5 lsb {1 lsb (n - 1) + 0.5 lsb} actual conversion characteristics (actually-measured value) actual conversion characteristics ideal characteristics digital output analog input total error total error of digital output n = v nt - {1 lsb (n - 1) + 0.5 lsb} 1 lsb [lsb] 1 lsb = (ideal value) avrh - av ss 1024 [v] v ot (ideal value) = av ss + 0.5 lsb [v] v fst (ideal value) = avrh - 1.5 lsb [v] v nt : a voltage at which digital output transitions from (n - 1) to n.
mb90350 series 60 (continued) 3ff 3fe 3fd 004 003 002 001 av ss avrh av ss avrh n + 1 n n - 1 n - 2 v ot ( actual measurement value ) {1 lsb (n - 1) + v ot } actual conversion characteristics v fst (actual measurement value) v nt (actual measurement value) actual conversion characteristics ideal characteristics actual conversion characteristics actual conversion characteristics ideal characteristics digital output digital output analog input analog input v nt (actual measurement value) v (n + 1) t (actual measurement value) non linearity error differential linearity error non linearity error of digital output n = v nt - {1 lsb (n - 1) + v ot } 1 lsb [lsb] differential linearity error of digital output n = v ( n+1 ) t - v nt 1 lsb - 1 lsb [lsb] v fst - v ot 1022 [v] 1 lsb = v ot : voltage at which digital output transits from 000 h to 001 h . v fst : voltage at which digital output transits from 3fe h to 3ff h .
mb90350 series 61 7. notes on a/d converter section use the device with external circuits of the following output impedance for analog inputs : recommended output impedance of external circuits are : approx. 1.5 k w or lower (4.0 v av cc 5.5 v, sampling period 0.5 m s) if an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high as internal capacitor. if output impedance of an external circuit is too high, a sampling period for an analog voltage may be insufficient. 8. flash memory program/erase characteristics * : this value comes from the technology qualification. (using arrhenius equation to translate high temperature measurements into normalized value at + 85 c) parameter conditions value unit remarks min typ max sector erase time t a = + 25 c v cc = 5.0 v ? 115s excludes programming prior to erasure chip erase time ? 9 ? s excludes programming prior to erasure word (16 bit width) programming time ? 16 3,600 m s except for the overhead time of the system program/erase cycle ? 10,000 ?? cycle flash data retention time average t a = + 85 c 20 ?? years * c comparator analog input r 4.5 v av cc 5.5 v : r : = 2.52 k w , c : = 10.7 pf 4.0 v av cc < 4.5 v : r : = 13.6 k w , c : = 10.7 pf ? analog input circuit model note : use the values in the figure only as a guideline.
mb90350 series 62 n n n n ordering information part number package remarks mb90f352pfm 64-pin plastic lqfp (fpt-64p-m09) MB90F352SPFM mb90352pfm 64-pin plastic lqfp (fpt-64p-m09) mb90352spfm mb90v340a-101 299-pin ceramic pga (pga-299c-a01) for evaluation mb90v340a-102
mb90350 series 63 n n n n package dimensions 64-pin plastic lqfp (fpt-64p-m09) note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness including plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parentheses are reference values. c 2003 fujitsu limited f64018s-c-3-5 0.65(.026) 0.10(.004) 116 17 32 49 64 33 48 12.000.10(.472.004)sq 14.000.20(.551.008)sq index 0.320.05 (.013.002) m 0.13(.005) 0.1450.055 (.0057.0022) "a" .059 C.004 +.008 C0.10 +0.20 1.50 0~8 ? 0.25(.010) (mounting height) 0.500.20 (.020.008) 0.600.15 (.024.006) 0.100.10 (.004.004) details of "a" part (stand off) 0.10(.004) *
mb90350 series fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0405 ? fujitsu limited printed in japan

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